Misc is actually the first four letters of English miscellaneous, which means miscellaneous, mixed and mixed. You can see the file or function name related to misc in the source code of Linux. Using misc to name the file mainly means that the file has not been classified. I don't know which aspect it belongs to or where it is better to place it, so we temporarily use misc. For example, under the folder include linux , there is a miscdevice H Header file; Variable names or functions prefixed with misc are often encountered in code. MISC (Mobile Information Service Center) is the first technical support platform developed by Zhuowang Group for mobile operators for the smooth implementation of the Dream Plan. She has realized the effective support and business management of the open value chain "service provider>network operator>user" business model, involving SP management, service management, user management, subscription management, billing management, statistical analysis and many other fields of operation. It is the core management platform for operators to provide data service for customers in the new network environment.

But in the field of CTF, Misc only expresses the first meaning. Qsnctf {e20491a9-97ad-404a-9f29-0810bd5c491e} MISC (Macro Instruction Set Computer) macro instruction set architecture computer. In 1985, Beijing Duosi Software Co., Ltd. proposed and organized the development of a new generation of computer CPU architecture. It was named by Academician Zhang Xiaoxiang in 1988. In 1993, following the previous research results of MISC, Beijing Duosi Technology Industrial Park Co., Ltd. developed 64 bit high-performance MISC general-purpose CPU chips, and Beijing Nansida Technology Development Co., Ltd. developed high-performance MISC security general-purpose CPU chips. After ten years of practice, the MISC technology system was improved.

MISC technical system includes:

1) VLMIW (Variable Length Macro Instruction Word Architecture)

2) EHCC (Explicitly Hardware Cell Controlling)

3) ESOC (Elements Level System on chip)

4) ICKH (IC Design Know How)

1. VLMIW

The variable length macro instruction architecture technology reveals a unique design that uses the ultra long instruction control architecture to realize static and dynamic reorganization of simple and symmetrical component structures and redefine their operating relationships, so that the architecture can be recombined according to specific applications, and each combination will enable the macro language supported by the ultra long instruction control architecture used by the microprocessor, In essence, it is close to the human demand for computer operation behavior, that is, the macro instructions actually run by the microprocessor directly reflect the semantic, grammatical and pragmatic relationships of high-level language elements, and support high-level semantic operations of high-level languages.

Variable length macro instruction architecture technology uses operators as instruction components to form high-level semantics, and supports parallel operation of complex instruction functions through macro instruction processing technology; It supports the expansion of complex instruction functions through explicit, implicit, backup instruction forms and 3D decoders.

1.1 Macro Processing (IMP)

Through the methods of assembly, delay, replacement and sorting, the operator or macro instruction components are orderly combined into a single cycle instruction code stream to maximize the use of instruction bandwidth and improve the parallelism of operations.

Queuing: processing the relationship between serial and parallel operations of instructions, including the sorting of explicit, implicit and backup instructions. By using this instruction to control the sorting method and device, data related or operation related instruction components can be designed in a control instruction for sorting operation, so that the serial operation is continuous and parallel with other operations. This reduces the occupation of instruction space, which reduces the demand for instruction cache and reduces the fetching cycle.

Combination: processing of instruction parallel operation relationship, including assembly of carrying instructions and implicit or explicit instructions. Through the instruction control assembly method and device, the instruction components of the related serial operation process and parallel operation can be assembled into one instruction, and the assembled instruction components can be executed serially or in parallel according to the requirements of the instruction sequence. Thus, the program design is simplified, and the operation throughput can be increased without increasing the machine bus width, the execution time of each instruction and the delay of the decoding control circuit.

Delay technology: preprocess subsequent instructions, and make them realize parallel processing relationship during operation. This includes the latency of explicit, implicit, and backup instructions. By using the instruction to control the delay method and device, the idle instruction encoding segment in the instruction is used to add the delay encoding of the instruction component of the subsequent operation, so that the delay instruction encoding is parallel to the operation instruction during execution. Under the condition that the machine bus width is unchanged, the codes exceeding the machine bus width can participate in the control at the same time.

Substitution: parallel operation relation processing of explicit, implicit and backup instructions. Through the instruction control replacement method and device, a repeated operation code can be separated from the instruction word sequence in the process of multi cycle operation and executed independently, the instruction flow sequence can be reduced, and the width of the instruction can be dynamically increased.

1.2 Mixed mode register architecture RCREG (Recombinatory Register)

The register architecture consists of stack, queue, register and memory operations, which supports multi syntax operations, data storage structure reorganization and register reuse operations. include:

1. Operation mode conversion: through dynamic or static instruction component settings, the operation mode of registers can be changed (stack, queue, register, memory operation mode selection), and multi syntax operations (prefix, infix, suffix) are supported;

2. Architecture replacement: through dynamic or static instruction component settings, the register architecture (master replica register structure, window register structure, and rotation register structure) can be changed to support the operation of the breeding register stack system.

3. Control instruction link: the operator is linked to the instruction configuration file through macro processing to achieve architecture replacement.

1.3 Three dimensional decoding system 3RDec (3-Route Instruction Decoder)

The decoder architecture of MISC architecture is designed according to the requirements of human behavior operation.

The characteristics of MISC architecture decoder are as follows: master-slave decoding control mode; Independent parallel control mode; Independent serial control mode; Parallel serial hybrid control mode;

There are reorganization and macro processing modes in the decoder of MISC architecture, which can be sorted, assembled, replaced and delayed. There are parallel, serial, priority and waiting execution modes.

MISC architecture decoder system includes: master decoder (related control decoder), slave decoder (including independent decoder, three-dimensional decoder, bus control decoder, interface decoder, etc.)

Correlation decoding: It is a typical master-slave decoding control mode. Its main decoder implements the decoding of instruction form, and its slave decoder implements the decoding of instruction format or operator format. Feature: Implicit and explicit interaction.

Independent decoding: It refers to the decoder that can decode multiple instruction formats in parallel or in series. The master and slave decoder can control the slave decoder by the master decoder to complete the instruction decoding control. Independent decoders can be designed into the same or different decoding systems, and the main decoder controls the allocation of decoders. The main function is to decode various instruction formats. include:

1. The same decoding system: all instruction formats are decoded through this decoding system.

2. Different decoding systems: different instruction formats are decoded by corresponding decoding system decoders.

3. Master slave control: the master decoder assigns the same or different decoding systems to the instruction formats carried by the instruction forms, and performs decoding.

4. Independent parallel control: the decoding systems are arranged in order according to different instruction formats carried by the instruction form, and the same or different decoding systems are used for decoding execution. Features: Explicit control.

Three dimensional decoder system: it refers to that explicit instructions, implicit instructions and backup instruction structures can be decoded in parallel and serial (Boolean form) together; The 3D decoder can complete decoding under the control of related decoders, and organize the decoding system of MISC system together with other independent decoders, including bus control decoder, memory control decoder, dedicated IO control decoder, security decoder, cyclic mobile pipeline decoder and other multiple decoder devices. Its characteristics:

The 3D decoder device mainly controls the encoding of multiple instruction configuration files and supports the decoding of multiple instruction configuration files; Forming a decoding control flow that can be executed continuously, and supporting the optimized decoding of parallel and serial operations of instructions; Realize the requirements of the maximum optimized decoding design, and support the implementation of the optimized compiler algorithm. include:

1. Boolean operation relationship: 3D decoder can realize parallel (independent), serial (related) or null operation (delay)

2. Time sharing operation relationship: according to Boolean operation relationship, time sharing and constraint operation functions of instruction flow can be established

3. Exception handling: independent implementation of parallel exception handling and operation of the system

4. Multiple configuration files: multiple configuration files are decoded at the same time, converted and optimized to form a high-speed internal instruction stream

1.4 Explicit, Implicit, Backup Instruction Type 3IT (Explicit_Implicit_Reserve Instruction Type)

Explicit instruction form is the complete target instruction structure that constitutes an algorithm or operation.

Implicit instructions are instruction structures that cooperate with explicit instructions to implement macro operations, loop operations or branch preprocessing operations in an algorithm or operation.

The backup instruction is an instruction structure that combines explicit and implicit instructions to preload and delay the static control macro instructions, loop programs, branch preprocessors used in the algorithm.

Static instructions (implicit, explicit, backup) are out of order. The instructions are arranged out of order. Backup instructions are loaded by explicit or implicit instructions, and implicit instructions are loaded during execution.

Delay operation of backup instructions: backup instructions are static instructions, preloaded, executed according to current instructions, drive decoding, and delay operation.

Implicit instruction operation reuse: In explicit instruction execution, establish implicit instruction stream (backup). When macro instructions or loop instructions or branch preprocessing operations are executed repeatedly, they are controlled by implicit instruction flow operations.

1.5 Macro Instruction Static and Dynamic Configuration Format

When initializing, the static configuration file of macro instructions is loaded into the architecture to identify the reorganization of architecture resources and connection relationships.

The dynamic configuration file of macro instructions controls the operation relationship of the architecture during execution, and realizes the function of macro instructions.

Static configuration file: it is the initialization code for the explicit hardware control unit to realize the architecture reorganization. The code indicates the occupancy of resources and the connection relationship between resources.

Dynamic configuration file: It is the execution code of the explicit hardware control unit to realize the architecture operation reorganization. This encoding indicates that the architecture implements the operation of the macro instruction.

2. Explicit hardware unit control technology EHCC

The resource, network and other control components in the architecture are directly oriented to the instruction macro processing system, so that it can realize hardware unit reconfiguration, operation method reorganization and instruction semantics reproduction according to application requirements and macro processing technology.

2.1 Reconfigurable Logical Architecture (RCA)

According to the description of a certain kind of algorithm space, the architecture design supporting multiple algorithm operations can be realized. This design reflects the characteristics of FPGA logic reconstruction, DSP programming method and ASIC execution efficiency. Under the control of COS system to MISC macro instruction configuration file, the special design of general chip is realized.

Cluster Overlay Technology of Operation and Resources (Tricolor Analysis)

Static and dynamic configuration: network connection technology; It supports instruction reproduction and component reuse to achieve small-scale circuit and functional scalability.

Controllable node coding: The instruction component corresponds to the controllable node of the hardware unit, which realizes the architecture reorganization IP design and integration.

2.2 Static and Dynamic Identifier System (SDI)

The instruction configuration file includes static configuration file and dynamic configuration file. Each configuration file contains the instruction format and macro processing operator of MISC macro instructions.

Static configuration file: it is the initialization code for the explicit hardware control unit to realize the architecture reorganization. The code indicates the occupancy of resources and the connection relationship between resources.

Dynamic configuration file: It is the execution code of the explicit hardware control unit to realize the architecture operation reorganization. This encoding indicates that the architecture implements the operation of the macro instruction.

2.3 Direct and Indirect Connected Net

The direct connection network characterizes the best efficiency between resources.

Indirect connection network depicts the optimal area of resources.

Some direct and some indirect connected networks depict the optimization principles of design.

The least connected network and fully connected optimal design techniques characterize the adaptability and scalability of the algorithm.

2.4 Master and Slavery Control (MSC)

Reuse control technology for resources (registers or functional parts) to reduce circuit area and improve resource utilization. Including: register resource reuse, data reuse, functional unit reuse, multi operation functional unit reuse and multi functional unit control.

2.5 Architecture and Instruction Transformation (AIT)

Replacement technology can convert the object code of one architecture or one instruction set into the object code of another architecture or instruction set. The important design basis of replacement technology is reconfigurable logic.

Semantic replacement: replacement of resources, operations and functions

Syntax replacement: replacement of data connection relationship and data network

Pragmatic replacement: the replacement of structure and resources

Symbol replacement: replacement of code and operation

3. Unit level system integration design technology ESOC